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?2003 silicon storage technology, inc. s71077-05-000 3/03 310 1 the sst logo and superflash are registered trademarks of silicon storage technology, inc. ssf is a trademark of silicon storage technology, inc. these specifications are subject to change without notice. data sheet 4 mbit (512k x8) superflash eeprom sst28sf040a / sst28vf040a features: ? single voltage read and write operations ? 4.5-5.5v-only for sst28sf040a ? 2.7-3.6v for sst28vf040a superior reliability ? endurance: 100,000 cycles (typical) ? greater than 100 years data retention memory organization: 512k x8 sector-erase capability: 256 bytes per sector low power consumption ? active current: 15 ma (typical) for 5.0v and 10 ma (typical) for 2.7-3.6v ? standby current: 5 a (typical) fast sector-erase/byte-program operation ? byte-program time: 35 s (typical) ? sector-erase time: 2 ms (typical) ? complete memory rewrite: 20 sec (typical) fast read access time ? 4.5-5.5v-only operation: 90 and 120 ns ? 2.7-3.6v operation: 150 and 200 ns latched address and data hardware and software data protection ? 7-read-cycle-sequence software data protection end-of-write detection ? toggle bit ? data# polling ttl i/o compatibility jedec standard ? flash eeprom pinouts packages available ? 32-lead plcc ? 32-lead tsop (8mm x 20mm) ? 32-pin pdip product description the sst28sf/vf040a are 512k x8 bit cmos sector- erase, byte-program eeproms. the sst28sf/vf040a are manufactured using sst?s proprietary, high perfor- mance cmos superflash eeprom technology. the split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternative approaches. the sst28sf/vf040a erase and program with a single power supply. the sst28sf/ vf040a conform to jedec standard pinouts for byte wide memories and are compatible with existing industry stan- dard flash eeprom pinouts. featuring high performance programming, the sst28sf/ vf040a typically byte-program in 35 s. the sst28sf/ vf040a typically sector-erase in 2 ms. both program and erase times can be optimized using interface features such as toggle bit or data# polling to indicate the completion of the write cycle. to protect against an inadvertent write, the sst28sf/vf040a have on chip hardware and software data protection schemes. designed, manufactured, and tested for a wide spectrum of applications, the sst28sf/ vf040a are offered with a guaranteed sector endurance of 10,000 cycles. data retention is rated greater than 100 years. the sst28sf/vf040a are best suited for applications that require re-programmable nonvolatile mass storage of pro- gram, configuration, or data memory. for all system appli- cations, the sst28sf/vf040a significantly improve performance and reliability, while lowering power consump- tion when compared with floppy diskettes or eprom approaches. flash eeprom technology makes possible convenient and economical updating of codes and control programs on-line. the sst28sf/vf040a improve flexibil- ity, while lowering the cost of program and configuration storage application. the functional block diagram shows the functional blocks of the sst28sf/vf040a. figures 1, 2, and 3 show the pin assignments for the 32-lead plcc, 32-lead tsop, and 32- pin pdip packages. pin descriptions and operation modes are described in tables 2 through 5. device operation commands are used to initiate the memory operation func- tions of the device. commands are written to the device using standard microprocessor write sequences. a com- mand is written by asserting we# low while keeping ce# low. the address bus is latched on the falling edge of we# or ce#, whichever occurs last. the data bus is latched on the rising edge of we# or ce#, whichever occurs first. note, during the software data protection sequence the addresses are latched on the rising edge of oe# or ce#, whichever occurs first. sst28sf / vf040a4mb (x8) byte-program, small erase sector flash memories
2 data sheet 4 mbit superflash eeprom sst28sf040a / sst28vf040a ?2003 silicon storage technology, inc. s71077-05-000 3/03 310 command definitions table 4 contains a command list and a brief summary of the commands. the following is a detailed description of the operations initiated by each command. sector-erase the sector-erase operation erases all bytes within a sector and is initiated by a setup command and an execute com- mand. a sector contains 256 bytes. this sector erasability enhances the flexibility and usefulness of the sst28sf/ vf040a, since most applications only need to change a small number of bytes or sectors, not the entire chip. the setup command is performed by writing 20h to the device. the execute command is performed by writing d0h to the device. the erase operation begins with the rising edge of the we# or ce#, whichever occurs first and terminates automatically by using an internal timer. the end-of-erase can be determined using either data# polling, toggle bit, or successive reads detection meth- ods. see figure 9 for timing waveforms. the two-step sequence of a setup command followed by an execute command ensures that only memory contents within the addressed sector are erased and other sectors are not inadvertently erased. sector-erase flow chart description fast and reliable erasing of the memory contents within a sector is accomplished by following the sector-erase flow- chart as shown in figure 18. the entire procedure consists of the execution of two commands. the sector-erase oper- ation will terminate after a maximum of 4 ms. a reset com- mand can be executed to terminate the sector-erase operation; however, if the erase operation is terminated prior to the 4 ms time-out, the sector may not be fully erased. a sector-erase command can be reissued as many times as necessary to complete the erase operation. the sst28sf/vf040a cannot be over-erased. chip-erase the chip-erase operation is initiated by a setup command (30h) and an execute command (30h). the chip-erase operation allows the entire array of the sst28sf/vf040a to be erased in one operation, as opposed to 2048 sector- erase operations. using the chip-erase operation will mini- mize the time to rewrite the entire memory array. the chip- erase operation will terminate after a maximum of 20 ms. a reset command can be executed to terminate the erase operation; however, if the chip-erase operation is termi- nated prior to the 20 ms time-out, the chip may not be com- pletely erased. if an erase error occurs a chip-erase command can be reissued as many times as necessary to complete the chip-erase operation. the sst28sf/ vf040a cannot be over-erased. (see figure 8) byte-program the byte-program operation is initiated by writing the setup command (10h). once the program setup is per- formed, programming is executed by the next we# pulse. see figures 5 and 6 for timing waveforms. the address bus is latched on the falling edge of we# or ce#, whichever occurs last. the data bus is latched on the rising edge of we# or ce#, whichever occurs first, and begins the program operation. the program opera- tion is terminated automatically by an internal timer. see figure 16 for the programming flowchart. the two-step sequence of a setup command followed by an execute command ensures that only the addressed byte is programmed and other bytes are not inadvertently programmed. the byte-program fl owchart description programming data into the sst28sf/vf040a is accom- plished by following the byte-program flowchart shown in figure 16. the byte-program command sets up the byte for programming. the address bus is latched on the falling edge of we# or ce#, whichever occurs last. the data bus is latched on the rising edge of we# or ce#, whichever occurs first and begins the program operation. the end of program can be detected using either the data# polling, toggle bit, or successive reads. reset the reset command is provided as a means to safely abort the erase or program command sequences. follow- ing either setup command (erase or program) with a write of ffh will safely abort the operation. memory contents will not be altered. after the reset command, the device returns to the read mode. the reset command does not enable software data protection. see figure 7 for timing waveforms. read the read operation is initiated by setting ce#, and oe# to logic low and setting we# to logic high (see table 3). see figure 4 for read cycle timing waveform. the read opera- tion from the host retrieves data from the array. the device remains enabled for read until another operation mode is accessed. during initial power-up, the device is in the read mode and is software data protected. the device must be unprotected to execute a write command.
data sheet 4 mbit superflash eeprom sst28sf040a / sst28vf040a 3 ?2003 silicon storage technology, inc. s71077-05-000 3/03 310 the read operation of the sst28sf/vf040a are con- trolled by oe# and ce# at logic low. when ce # is high, the chip is deselected and only standby power will be con- sumed. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when ce# or oe# are high. read-id the read-id operation is initiated by writing a single com- mand (90h). a read of address 0000h will output the man- ufacturer?s id (bfh). a read of address 0001h will output the device id (04h). any other valid command will termi- nate this operation. data protection in order to protect the integrity of nonvolatile data storage, the sst28sf/vf040a provide both hardware and software features to prevent inadvertent writes to the device, for example, during system power-up or power-down. such provisions are described below. hardware data protection the sst28sf/vf040a are designed with hardware fea- tures to prevent inadvertent writes. this is done in the fol- lowing ways: 1. write cycle inhibit mode: oe# low, ce#, or we# high will inhibit the write operation. 2. noise/glitch protection: a we# pulse width of less than 5 ns will not initiate a write cycle. 3. v dd power up/down detection: the write opera- tion is inhibited when v dd is less than 2.0v. 4. after power-up, the device is in the read mode and the device is in the software data protect state. software data protection (sdp) the sst28sf/vf040a have software methods to further prevent inadvertent writes. in order to perform an erase or program operation, a two-step command sequence con- sisting of a set-up command followed by an execute com- mand avoids inadvertent erasing and programming of the device. the sst28sf/vf040a will default to software data pro- tection after power up. a sequence of seven consecutive reads at specific addresses will unprotect the device the address sequence is 1823h, 1820h, 1822h, 0418h, 041bh, 0419h, 041ah. the address bus is latched on the rising edge of oe# or ce#, whichever occurs first. a similar seven read sequence of 1823h, 1820h, 1822h, 0418h, 041bh, 0419h, 040ah will protect the device. also refer to figures 10 and 11 for the 7 read cycle sequence software data protection. the i/o pins can be in any state (i.e., high, low, or tri-state). write operation status detection the sst28sf/vf040a provide three means to detect the completion of a write operation, in order to optimize the system write operation. the end of a write operation (erase or program) can be detected by three means: 1) monitoring the data# polling bit, 2) monitoring the toggle bit, or 3) by two successive reads of the same data. these three detection mechanisms are described below. the actual completion of the nonvolatile write is asynchro- nous with the system; therefore, either a data# polling or toggle bit read may be simultaneous with the completion of the write cycle. if this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to con- flict with the dq used. in order to prevent spurious rejec- tion, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the device has completed the write cycle, otherwise the rejec- tion is valid. data# polling (dq 7 ) the sst28sf/vf040a feature data# polling to indi- cate the write operation status. during a write opera- tion, any attempt to read the last byte loaded during the byte-load cycle will receive the complement of the true data on dq 7 . once the write cycle is completed, dq 7 will show true data. note that even though dq 7 may have valid data immediately following the comple- tion of an internal write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive read cycles after an interval of 1 s. see figure 12 for data# polling timing waveforms. in order for data# polling to function correctly, the byte being polled must be erased prior to programming. toggle bit (dq 6 ) an alternative means for determining the write operation status is by monitoring the toggle bit, dq 6 . during a write operation, consecutive attempts to read data from the device will result in dq 6 toggling between logic 0 (low) and logic 1 (high). when the write cycle is completed, the tog- gling will stop. the device is then ready for the next opera- tion. see figure 13 for toggle bit timing waveforms.
4 data sheet 4 mbit superflash eeprom sst28sf040a / sst28vf040a ?2003 silicon storage technology, inc. s71077-05-000 3/03 310 successive reads an alternative means for determining an end of a write operation is by reading the same address for two consecu- tive data matches. product identification the product identification mode identifies the device as sst28sf/vf040a and the manufacturer as sst. this mode may be accessed by hardware and soft- ware operations. the hardware operation is typically used by an external programmer to identify the correct algorithm for the sst28sf/vf040a. users may wish to use the software operation to identify the device (i.e., using the device id). for details see table 3 for the hardware operation and figure 19 for the software operation. the manufacturer?s and device ids are the same for both operations. figure 1: p in a ssignments for 32- lead plcc table 1: p roduct i dentification address data manufacturer?s id 0000h bfh device id sst28sf/vf040a 0001h 04h t1.1 310 y-decoder i/o buffers and data latches 310 ill b1.1 address buffer & latches x-decoder dq 7 - dq 0 a 18 - a 0 we# oe# ce# superflash memory control logic f unctional b lock d iagram 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 a7 a6 a5 a4 a3 a2 a1 a0 dq0 a14 a13 a8 a9 a11 oe# a10 ce# dq7 4 3 2 1 32 31 30 a12 a15 a16 a18 v dd we# a17 32-lead plcc top view 310 ill f02.3 14 15 16 17 18 19 20 dq1 dq2 v ss dq3 dq4 dq5 dq6
data sheet 4 mbit superflash eeprom sst28sf040a / sst28vf040a 5 ?2003 silicon storage technology, inc. s71077-05-000 3/03 310 figure 2: p in a ssignments for 32- lead tsop figure 3: p in a ssignments for 32- pin pdip a11 a9 a8 a13 a14 a17 we# v dd a18 a16 a15 a12 a7 a6 a5 a4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 oe# a10 ce# dq7 dq6 dq5 dq4 dq3 v ss dq2 dq1 dq0 a0 a1 a2 a3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 310 ill f01.2 standard pinout top view die up 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-pin pdip top view 310 ill f19.0 a18 a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 v ss 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 v dd we# a17 a14 a13 a8 a9 a11 oe# a10 ce# dq7 dq6 dq5 dq4 dq3 table 2: p in d escription symbol pin name functions a 18 -a 8 row address inputs to provide memory addresses. row addresses define a sector. a 7 -a 0 column address inputs selects the byte within the sector dq 7 -dq 0 data input/output to output data during read cycles and receive input data during write cycles. data is internally latched during a write cycle. the outputs are in tri-state when oe# or ce# is high. ce# chip enable to activate the device when ce# is low. 1 oe# output enable to gate the data output buffers. we# write enable to control the write operations. 1 v dd power supply to provide: 5.0v supply (4.5-5.5v) for sst28sf040a 2.7v supply (2.7-3.6v) for sst28vf040a v ss ground t2.2 310 1. this pin has an internal pull-up resistor.
6 data sheet 4 mbit superflash eeprom sst28sf040a / sst28vf040a ?2003 silicon storage technology, inc. s71077-05-000 3/03 310 table 3: o peration m odes s election mode ce# oe# we# dq address read v il v il v ih d out a in byte-program v il v ih v il d in a in, see table 4 sector-erase v il v ih v il d in a in, see table 4 standby v ih x 1 x high z x write inhibit x v il x high z/ d out x xxv ih high z/ d out x software chip-erase v il v ih v il d in see table 4 product identification hardware mode v il v il v ih manufacturer?s id (bfh) device id (04h) a 18 -a 1 =v il , a 9 =v h , a 0 =v il a 18 -a 1 =v il , a 9 =v h , a 0 =v ih software mode v il v il v ih see table 4 sdp enable & disable mode v il v il v ih see table 4 reset v il v ih v il see table 4 t3.4 310 1. x can be v il or v ih , but no other value. table 4: s oftware c ommand s ummary command summary required setup command cycle execute command cycle cycle(s) type 1 1. type definition: w = write, r = read, x can be v il or v ih , but no other value. addr 2,3 2. addr (address) definition: sa = sector address = a 18 -a 8 , sector size = 256 bytes; a 7 -a 0 = x for this command. 3. addr (address) definition: pa = program address = a 18 -a 0 . data 4 4. data definition: pd = program data, h = number in hex. type 1 addr 2,3 data 4 sdp 5 5. sdp = software data protect mode using 7 read cycle sequence. a) y = the operation can be ex ecuted with protection enabled b) n = the operation cannot be executed with protection enabled sector-erase 2 w x 20h w sa d0h n byte-program 2 w x 10h w pa pd n chip-erase 6 6. the chip-erase function is not s upported on industrial temperature parts. 2 w x 30h w x 30h n reset 1 w x ffh y read-id 2 w x 90h r 7 7. address 0000h retrieves the manufacturer?s id of bfh and address 0001h retrieves the device id of 04h. 7 y software data protect 7 r 8 8. refer to figure 11 for the 7 read cycle sequence for software-data-protect. software data unprotect 7 r 9 9. refer to figure 10 for the 7 read cycl e sequence for software-data-unprotect. t4.4 310 table 5: m emory a rray d etail sector select byte select a 18 - a 8 a 7 - a 0 t5.0 310
data sheet 4 mbit superflash eeprom sst28sf040a / sst28vf040a 7 ?2003 silicon storage technology, inc. s71077-05-000 3/03 310 absolute maximum stress ratings (applied conditions greater than those listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. exposure to absolute maximum stress rating conditions may affect device reliability.) temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0. 5v to v dd +0.5v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0v to v dd +2.0v voltage on a 9 pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 14.0v package power dissipation capability (ta = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w through hold lead soldering temperature (10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300c surface mount lead soldering temperature (3 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240c output short circuit current 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 m a 1. outputs shorted for no more than one second. no more than one output shorted at a time. o perating r ange for sst28sf040a range ambient temp v dd commercial 0c to +70c 4.5-5.5v industrial -40c to +85c 4.5-5.5v o perating r ange for sst28vf040a range ambient temp v dd commercial 0c to +70c 2.7-3.6v industrial -40c to +85c 2.7-3.6v ac c onditions of t est input rise/fall time . . . . . . . . . . . . . . 10 ns output load . . . . . . . . . . . . . . . . . . . . . 1 ttl gate andc l = 100 pf for sst28sf040a c l = 100 pf for sst28vf040a see figures 14 and 15
8 data sheet 4 mbit superflash eeprom sst28sf040a / sst28vf040a ?2003 silicon storage technology, inc. s71077-05-000 3/03 310 table 6: dc o perating c haracteristics for sst28sf040a symbol parameter limits test conditions min max units i dd power supply current address input=v ilt /v iht, at f=1/t rc min, v dd =v dd max read 32 ma ce#=oe#=v il , we#=v ih , all i/os open program and erase 40 ma ce#=we#=v il , oe#=v ih , v dd =v dd max i sb1 standby v dd current (ttl input) 3mace#=v ih , v dd =v dd max i sb2 standby v dd current (cmos input) 20 a ce#=v dd -0.3v, v dd =v dd max i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 10 a v out =gnd to v dd , v dd =v dd max v il input low voltage 0.8 v v dd =v dd min v ih input high voltage 2.0 v v dd =v dd max v ol output low voltage 0.4 v i ol =2.1 ma, v dd =v dd min v oh output high voltage 2.4 v i oh =-400 a, v dd =v dd min v h supervoltage for a 9 11.6 12.4 v ce#=oe#=v il , we#=v ih i h supervoltage current for a 9 200 a ce#=oe#=v il , we#=v ih , a 9 =v h max t6.5 310 table 7: dc o perating c haracteristics for sst28vf040a symbol parameter limits test conditions min max units i dd power supply current address input=v ilt /v iht, at f=1/t rc min, v dd =v dd max read 10 ma ce#=oe#=v il , we#=v ih , all i/os open program and erase 25 ma ce#=we#=v il , oe#=v ih , v dd =v dd max i sb2 standby v dd current (cmos input) 20 a ce#=oe#=we#=v dd -0.3v, v dd =v dd max i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 10 a v out =gnd to v dd , v dd =v dd max v il input low voltage 0.8 v v dd =v dd min v ih input high voltage 2.0 v v dd =v dd max v ol output low voltage 0.4 v i ol =100 a, v dd =v dd min v oh output high voltage 2.4 v i oh =-100 a, v dd =v dd min v h supervoltage for a 9 11.6 12.4 v ce#=oe#=v il , we#=v ih i h supervoltage current for a 9 200 a ce#=oe#=v il , we#=v ih , a 9 =v h max t7.5 310
data sheet 4 mbit superflash eeprom sst28sf040a / sst28vf040a 9 ?2003 silicon storage technology, inc. s71077-05-000 3/03 310 table 8: r ecommended s ystem p ower - up t imings symbol parameter minimum units t pu-read 1 power-up to read operation 10 ms t pu-write 1 power-up to write operation 10 ms t8.4 310 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. table 9: c apacitance (ta = 25c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. i/o pin capacitance v i/o = 0v 12 pf c in 1 input capacitance v in = 0v 6 pf t9.0 310 table 10: r eliability c haracteristics symbol parameter minimum specification units test method n end 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t10.7 310
10 data sheet 4 mbit superflash eeprom sst28sf040a / sst28vf040a ?2003 silicon storage technology, inc. s71077-05-000 3/03 310 ac characteristics table 11: r ead c ycle t iming p arameters for sst28sf040a ieee symbol industry symbol parameter sst28sf040a-90 sst28sf040a-120 units min max min max tavav t rc read cycle time 90 120 ns tavqv t aa address access time 90 120 ns telqv t ce chip enable access time 90 120 ns tglqv t oe output enable access time 45 50 ns tehqz t clz 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. ce# low to active output 0 0 ns tghqz t olz 1 oe# low to active output 0 0 ns telqx t chz 1 ce# high to high-z output 20 30 ns tglqx t ohz 1 oe# high to high-z output 20 30 ns taxqx t oh 1 output hold from address change 0 0 ns t11.6 310 table 12: r ead c ycle t iming p arameters for sst28vf040a ieee symbol industry symbol parameter sst28vf040a-150 sst28vf040a-200 units min max min max tavav t rc read cycle time 150 200 ns tavqv t aa address access time 150 200 ns telqv t ce chip enable access time 150 200 ns tglqv t oe output enable access time 75 100 ns tehqz t clz 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. ce# low to active output 0 0 ns tghqz t olz 1 oe# low to active output 0 0 ns telqx t chz 1 ce# high to high-z output 40 60 ns tglqx t ohz 1 oe# high to high-z output 40 60 ns taxqx t oh 1 output hold from address change 0 0 ns t12.5 310
data sheet 4 mbit superflash eeprom sst28sf040a / sst28vf040a 11 ?2003 silicon storage technology, inc. s71077-05-000 3/03 310 table 13: e rase /p rogram c ycle t iming p arameters ieee symbol industry symbol parameter sst28sf040a sst28vf040a units min max min max tava t bp byte-program cycle time 40 40 s twlwh t wp write pulse width (we#) 90 100 ns tavwl t as address setup time 10 10 ns twlax t ah address hold time 50 100 ns telwl t cs ce# setup time 0 0 ns twhex t ch ce# hold time 0 0 ns tghwl t oes oe# high setup time 10 20 ns twgl t oeh oe# high hold time 10 20 ns twleh t cp write pulse width (ce#) 90 100 ns tdvwh t ds data setup time 50 100 ns twhdx t dh data hold time 10 20 ns twhwl2 t se sector-erase cycle time 4 4 ms t rst 1 reset command recovery time 4 4 s twhwl3 t sce software chip-erase cycle time 20 20 ms tehel t cph ce# high pulse width 50 50 ns twhwl1 t wph we# high pulse width 50 50 ns t pcp 1 protect ce# or oe# pulse width 50 50 ns t pch 1 protect ce# or oe# high time 50 50 ns t pa s 1 protect address setup time 40 40 ns t pa h 1 protect address hold time 0 0 ns t13.6 310 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er.
12 data sheet 4 mbit superflash eeprom sst28sf040a / sst28vf040a ?2003 silicon storage technology, inc. s71077-05-000 3/03 310 figure 4: r ead c ycle t iming d iagram figure 5: we# c ontrolled b yte -p rogram c ycle t iming d iagram 310 ill f03.2 ce# address a 18-0 oe# we# dq 7-0 t clz t oh data va l i d data va l i d t olz t oe t ce t chz t ohz t rc t aa 310 ill f04.1 ce# oe# we# t dh t ds t oes t cs t as t ah t wp t wph t oeh t ch t ds t dh t bp address a 18-0 dq 7-0 byte-program setup command i0h data valid
data sheet 4 mbit superflash eeprom sst28sf040a / sst28vf040a 13 ?2003 silicon storage technology, inc. s71077-05-000 3/03 310 figure 6: ce# c ontrolled b yte -p rogram c ycle t iming d iagram figure 7: r eset c ommand t iming d iagram 310 ill f05.1 ce# oe# we# t dh t ds t oes t cph t as t ah t cs t ch t oeh t cp t ds t dh t bp address a 18-0 dq 7-0 byte-program setup command i0h data valid 310 ill f06.0 ce# oe# we# t ds t dh t rst address a 18-0 dq 7-0 ffh
14 data sheet 4 mbit superflash eeprom sst28sf040a / sst28vf040a ?2003 silicon storage technology, inc. s71077-05-000 3/03 310 figure 8: c hip -e rase t iming d iagram figure 9: s ector -e rase t iming d iagram 310 ill f07.0 ce# oe# we# t dh t ds t dh t sce t ds address a 18-0 dq 7-0 30h setup command execute command 30h 310 ill f08.0 ce# oe# we# t dh t ah t as a in t ds t dh t se t ds address a 18-0 dq 7-0 20h setup command execute command d0h
data sheet 4 mbit superflash eeprom sst28sf040a / sst28vf040a 15 ?2003 silicon storage technology, inc. s71077-05-000 3/03 310 figure 10: s oftware d ata u nprotect d isable t iming d iagram figure 11: s oftware d ata p rotect d isable t iming d iagram 310 ill f09.4 oe# ce# we# address t pa h t pa s t pch t pcp note: a. addresses are latched internally on the rising edge of: 1. oe# if ce# is kept at low all time. 2. ce# if oe# is kept at low all time. 3. the first pin to go high if both are toggled. b. above address values are in hex. c. addresses > a12 are "don't care" 1823 1820 1822 0418 041b 0419 041a 310 ill f10.4 oe# ce# we# address t pa h t pa s t pch t pcp note: a. addresses are latched internally on the rising edge of: 1. oe# if ce# is kept at low all time. 2. ce# if oe# is kept at low all time. 3. the first pin to go high if both are toggled. b. above address values are in hex. c. addresses > a12 are "don't care" 1823 1820 1822 0418 041b 0419 040a
16 data sheet 4 mbit superflash eeprom sst28sf040a / sst28vf040a ?2003 silicon storage technology, inc. s71077-05-000 3/03 310 figure 12: d ata # p olling t iming d iagram figure 13: t oggle b it t iming d iagram 310 ill f11.0 ce# oe# we# note d# t oe t oeh t ce t oes d# d address a 18-0 dq 7-0 note: this time interval signal can be t se or t bp depending upon the selected operation mode. d 310 ill f12.0 ce# oe# we# note two read cycles with same outputs t oeh t oe t oe t oes t ce t ce address a 18-0 dq 6 note: this time interval signal can be t se or t bp depending upon the selected operation mode.
data sheet 4 mbit superflash eeprom sst28sf040a / sst28vf040a 17 ?2003 silicon storage technology, inc. s71077-05-000 3/03 310 figure 14: ac i nput /o utput r eference w aveforms figure 15: a t est l oad e xample 310 ill f13.1 reference points output input v ht v lt v ht v lt v iht v ilt ac test inputs are driven at v iht (2.4v) for a logic ?1? and v ilt (0.4 v) for a logic ?0?. measurement reference points for inputs and outputs are v ht (2.0 v) and v lt (0.8 v). input rise and fall times (10% ? 90%) are <10 ns. note: v ht - v high te s t v lt - v low te s t v iht - v input high test v ilt - v input low test 310 ill f14.2 to tester to dut c l r l low r l high v dd
18 data sheet 4 mbit superflash eeprom sst28sf040a / sst28vf040a ?2003 silicon storage technology, inc. s71077-05-000 3/03 310 figure 16: b yte -p rogram f lowchart 310 ill f15.3 ye s no no no last address read end-of-write detection ye s data verifies? ye s programming completed? programming completed next address programming failure load address and data & start programming execute byte- program setup command initialize address start
data sheet 4 mbit superflash eeprom sst28sf040a / sst28vf040a 19 ?2003 silicon storage technology, inc. s71077-05-000 3/03 310 figure 17: w rite w ait o ptions 310 ill f16.2 no no read byte ye s ye s does dq 6 match? program/erase completed read same byte program/erase initiated toggle bit wait t bp or t se program/erase completed program/erase initiated internal timer read dq 7 is dq 7 = true data? program/erase completed program/erase initiated data# polling
20 data sheet 4 mbit superflash eeprom sst28sf040a / sst28vf040a ?2003 silicon storage technology, inc. s71077-05-000 3/03 310 figure 18: s ector -e rase f lowcharts 310 ill f17.5 no no no no ye s ye s ye s ye s last sector? verify ffh erase completed? last address? device erased execute two step sector-erase command increment byte address next sector address end-of-write detection read ffh from selected byte address initialize sector address start sector-erase completed erase error
data sheet 4 mbit superflash eeprom sst28sf040a / sst28vf040a 21 ?2003 silicon storage technology, inc. s71077-05-000 3/03 310 figure 19: s oftware p roduct id f low execute read id command (90h) to enter read-id mode read address 0000h mfg's id = sst (bfh) read address 0001h device id = 28sf040 (04h) execute reset command (ffh) to exit from read-id mode 310 ill f18.5
22 data sheet 4 mbit superflash eeprom sst28sf040a / sst28vf040a ?2003 silicon storage technology, inc. s71077-05-000 3/03 310 product ordering information valid combinations for sst28sf040a sst28sf040a-90-4c-nh sst28sf040a-90-4c-eh sst28sf040a-90-4c-ph sst28sf040a-120-4c-nh sst28sf040a-120-4c-eh sst28sf040a-120-4i-nh ? sst28sf040a-120-4i-eh ? valid combinations for sst28vf040a sst28vf040a-150-4c-nh sst28vf040a-150-4c-eh sst28vf040a-200-4c-nh* sst28vf040a-200-4c-eh* sst28vf040a-200-4i-nh* ? sst28vf040a-200-4i-eh* ? note: valid combinations are those products in mass production or will be in mass production. consult your sst sales representative to confirm availability of valid combinations and to determine availability of new combinations. * not recommended for new designs. ? the software chip-erase function is not supported by the industrial temperature part. please contact sst if you require this function for an industrial temperature part. non-pb: several devices in this data sheet are also offered in non-pb (no lead added) packages. the non-pb part number is simply the standard part number with the letter ?e? added to the end of the package code. the non-pb package codes corresponding to the packages listed above are nhe and ehe. device speed suffix1 suffix2 sst28x f 040a - xxx -x x -x x package modifier h = 32 leads or pins package type e = tsop (type 1, die up, 8mm x 20mm) n = plcc p = pdip temperature range c = commercial = 0c to +70c i = industrial = -40c to +85c minimum endurance 4 = 10,000 cycles read access speed 200 = 200 ns 150 = 150 ns 120 = 120 ns 90 = 90 ns function f = chip- or sector-erase byte- or word-program voltag e s = 4.5-5.5v v = 2.7-3.6v
data sheet 4 mbit superflash eeprom sst28sf040a / sst28vf040a 23 ?2003 silicon storage technology, inc. s71077-05-000 3/03 310 packaging diagrams 32- lead p lastic l ead c hip c arrier (plcc) sst p ackage c ode : nh .040 .030 .021 .013 .530 .490 .095 .075 .140 .125 .032 .026 .032 .026 .029 .023 .453 .447 .553 .547 .595 .585 .495 .485 .112 .106 .042 .048 .048 .042 .015 min. top view side view bottom view 1 232 .400 bsc 32-plcc-nh-3 note: 1. complies with jedec publication 95 ms-016 ae dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in inches (max/min). 3. dimensions do not include mold flash. maximum allowable mold flash is .008 inches. 4. coplanarity: 4 mils. .050 bsc .050 bsc optional pin #1 identifier .020 r. max. r. x 30?
24 data sheet 4 mbit superflash eeprom sst28sf040a / sst28vf040a ?2003 silicon storage technology, inc. s71077-05-000 3/03 310 32- lead t hin s mall o utline p ackage (tsop) 8 mm x 20 mm sst p ackage c ode : eh 0.15 0.05 20.20 19.80 18.50 18.30 0.70 0.50 8.10 7.90 0.27 0.17 1.05 0.95 32-tsop-eh-7 note: 1.complies with jedec publication 95 mo-142 bd dimensions, although some dimensions may be more stringent. 2.all linear dimensions are in millimeters (max/min). 3.coplanarity: 0.1 mm 4.maximum allowable mold flash is 0.15 mm at the package ends, and 0.25mm between leads. pin # 1 identifier 0. 50 bsc 1mm 1.20 max. detail 0.70 0.50 0?- 5?
data sheet 4 mbit superflash eeprom sst28sf040a / sst28vf040a 25 ?2003 silicon storage technology, inc. s71077-05-000 3/03 310 32- pin p lastic d ual i n - line p ins (pdip) sst p ackage c ode : ph table 14: r evision h istory number description date 04 2002 data book may 2002 05 removed wh package part number changes - see page 22 for additional information clarified the test conditions for v dd read current parameter in table 6 and table 7 on page 8 ? address input = v ilt /v iht mar 2003 32-pdip-ph-3 pin #1 identifier c l 32 1 base plane seating plane note: 1. complies with jedec publication 95 mo-015 ap dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in inches (max/min). 3. dimensions do not include mold flash. maximum allowable mold flash is .010 inches. .200 .170 7? 4 plcs. .600 bsc .100 bsc .150 .120 .022 .016 .065 .045 .080 .070 .050 .015 .075 .065 1.655 1.645 .012 .008 0? 15? .625 .600 .550 .530
26 data sheet 4 mbit superflash eeprom sst28sf040a / sst28vf040a ?2003 silicon storage technology, inc. s71077-05-000 3/03 310 silicon storage technology, inc. 1171 sonora court sunnyvale, ca 94086 telephone 408-735-9110 fax 408-735-9036 www.superflash.com or www.sst.com

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